The DS2148 is a complete selectable E1 or T1 Line Interface Unit (LIU) for short- and long-haul
applications. Throughout the data sheet, J1 is represented wherever T1 exists. Receive sensitivity adjusts
automatically to the incoming signal and can be programmed for 0dB to 12dB or 0dB to 43dB for E1
applications and 0dB to 30dB or 0dB to 36dB for T1 applications. The device can generate the necessary
G.703 E1 waveshapes in 75Ω or 120Ω applications and DSX-1 line build outs or CSU line build outs of 0dB, -7.5dB, -15dB, and -22.5dB for T1 applications. The crystal-less onboard jitter attenuator requires only a 2.048MHz MCLK for both E1 and T1 applications (with the option of using a 1.544MHz MCLK in T1 applications). The jitter attenuator FIFO is selectable to either 32 bits or 128 bits in depth and can
be placed in either the transmit or receive data paths. An X 2.048MHz output clock synthesized to RCLK
is available for use as a backplane system clock (where n = 1, 2, 4, or 8). The DS2148 has diagnostic
capabilities such as loopbacks and PRBS pattern generation/detection. 16-bit loop-up and loop-down
codes can be generated and detected. The device can be controlled via an 8-bit parallel muxed or
nonmuxed port, serial port or used in hardware mode. The device fully meets all of the latest E1 and T1
specifications including ANSI T1.403-1999, ANSI T1.408, AT&T TR 62411, ITU G.703, G.704, G.706,
G.736, G.775, G.823, I.431, O.151, O.161, ETSI ETS 300 166, JTG.703, JTI.431, JJ-20.1, TBR12,
TBR13, and CTR4.
关键特性
Complete E1, T1, or J1 line interface unit
(LIU)
Supports both long- and short-haul trunks
Internal software-selectable receive-side
termination for 75Ω/100Ω/120Ω
5V power supply
32-bit or 128-bit crystal-less jitter attenuator
requires only a 2.048MHz master clock for
both E1 and T1 with option to use 1.544MHz
for T1
Generates the appropriate line build outs,
with and without return loss, for E1 and
DSX-1 and CSU line build outs for T1
AMI, HDB3, and B8ZS, encoding/decoding
16.384MHz, 8.192MHz, 4.096MHz, or
2.048MHz clock output synthesized to
recovered clock
Programmable monitor mode for receiver
Loopbacks and PRBS pattern generation/
detection with output for received errors
Generates/detects in-band loop codes, 1 to 16
bits including CSU loop codes
8-bit parallel or serial interface with optional
hardware mode
Multiplexed and nonmultiplexed parallel bus
supports Intel or Motorola
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